A novel BIST approach for testing input/output buffers in FPGAs
Chen Lei, Zhang Zhi Quan, Wen Ping · 2009
A novel Built-In Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series FPGAs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been successfully implemented and verified on Xilinx Virtex series FPGA. Only total of eight configurations are required to completely built-in self test of the I/O buffers in Virtex series FPGA.