Parallel Decomposition in Logic Synthesis
Krzysztof Jasiński, Tadeusz Łuba, Jerzy Kalinowski · 1989
In this paper a new approach to logic synthesis in VLSI design, based on parallel decomposition, is proposed. The idea is to use an effective method for multiple-output function reduction to select a decomposition that yields minimal silicon area in the final implementation. Experimental results and assessment of this synthesis method are provided.