Rapid analysis of interprocessor communications on heterogeneous system architectures via parallel cache emulation
Jen-Jung Cheng, Shih‐Hao Hung, Chih-Wei Yeh · 2015
The recently proposed heterogeneous system architecture (HSA) specifications enable shared-memory-based interprocessor communications between CPU cores and GPU cores via a flat coherent address space and memory-based signals to reduce explicit data copy overheads. Since modern CPU/GPU cores are often designed with distributed caches, the interprocessor communications occur implicitly in the form of coherence traffics among the distributed caches and are hardly noticed by the programmers. Although existing cache simulators such as GEMS can help reveal the coherence traffics, they are extremely slow for large systems, where reducing interprocessor communications is often key to performance optimization.