Low Power VLSI Circuit Design with Efficient HDL Coding
Bishwajeet Pandey, Manisha Pattanaik · 2013
In this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE 14.2 and implemented on high performance Virtex-6 FPGA, XC6VLX240T device, -1 speed grade, FFG1156 package and ML605 board. User constraints file (ucf) and net list constraints design (ncd) file are taken into consideration with XPower 14.2 for power consumption analysis. We take two codes. Our first code maps the clock enable signal to LUTs then the power consumption is 3.423 Watt. Our second code maps the clock enable signal to control ports then the power consumption is 3.625 Watt. By changing mapping style, we reduce 6% power reduction and also reduce number of LUT and D flip-flop used in implementation leads to area efficient design. By efficiently mapping, we reduce power consumption in multiple of power reduction with single statements. The experimental result shows the power analysis of both HDL mapping code.