Silicon compiler for neuro-ASICs
J. Ouali, G. Saucier · 1990
A distributed, synchronous architecture for artificial neural networks is proposed. A basic processor is associated to a neuron and is able to perform autonomously all the steps of the learning and the relaxation phases. Data circulation is implemented by shifting techniques. Customization of the network is done by setting identification data in dedicated memory elements. The neuron has been implemented on silicon. It is shown that, in a silicon compiler environment, dedicated networks can be easily generated by cascading these elementary blocks