A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/)
Anh Dinh, R.J. Bolton, Ralph D. Mason · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2001
A low latency architecture to compute the multiplicative inverse and division in a finite field GF (2/sup m/) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2/sup l/) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.