Design of a 2 × 2 fault-tolerant switching element
Woei Lin, Chuan-lin Wu · ACM SIGARCH Computer Architecture News · 1982
This paper describes the architecture of a 2 × 2 fault-tolerant switching element which can be used to modularly construct interconnection networks for multi-processing and local computer networking. The switching element uses distributed control and circuit switching. Its good gate-to-pin ratio can facilitate VLSI implementation.