An 800Mhz cryptographic pairing processor in 65nm CMOS
Yang Li, Jun Shu Han, Shuai Wang, Dabin Fang, Xiaoyang Zeng · 2012
Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. An efficient implementation of pairings is usually critical for realizing a cryptographic scheme practically. This paper presents a high-performance pairing processor with a new combined Montgomery multiplier which implements the fundamental operations of Fp2multiplication efficiently. The processor is fabricated in TSMC 65nm CMOS process. The chip achieves 800MHz (1.2V) with 266.5mW power consumption and a core area of 2.51mm2, and computes an optimal Ate pairing (254-bit curve) in 0.64ms.