NoC Based Multiplier-Less Constant Geometry FFT Architecture
Neeli Rashmi Prasad, Indrajit Chakrabarti, Santanu Chattopadhyay · 2014
This paper reports the architecture of a Network-on-Chip (NoC) based constant geometry FFT (CGFFT). The twiddle factor complex multiplications have been realized using new distributed arithmetic (NEDA) blocks. The architecture, which contains four processing elements (PEs) that are mapped by considering the data flow between the stages of FFT, has been mapped on to a 2 × 2 mesh NoC. The known traffic pattern and known data source-destination locations have reduced the latency of the router by minimizing the buffer size. The architecture has been implemented using Xilinx Kintex7 FPGA and has been simulated using a cycle-accurate SystemC based simulator.