Design of a comparator tree based on reversible logic
Himanshu Thapliyal, Nagarajan Ranganathan, Ryan Ferreira · 2010
The existing design of reversible n-bit binary comparator that compares two n-bit numbers is a serial design [1] having the latency of O(n). In this work, we present a new reversible n-bit binary comparator based on binary tree structure that has the latency of O(log2(n)). The reversible designs are based on a new reversible gate called the TR gate, the improved quantum cost of which is also derived in this work. In the proposed reversible binary tree comparator each node consists of a 2-bit reversible binary comparator that can compare two 2-bit numbers x(xi, xi-1) and y(yi, yi-1), to generate two 1-bit outputs Y and Z. Y will be 1 if x(xi, xi-1)>; y(yi, yi-1), and Z will be 1 if x(xi, xi-1)i, yi-1). After careful analysis, we modified the logic equations of Y = x1y̅1 ⊕ kx0y̅0and Z =x̅1y1⊕ kx̅0y0to Y = x1y̅1⊕ kx0y̅0and Z = x̅1y1⊕ kx̅0y0, respectively. The replacement of + operator with ⊕ operator without affecting the functionality of the design helped us in reversible mapping of the equations of Y and Z on the third output of the TR gate which is R=AB̅̅ ⊕ C. Further, TR gate can also efficiently generate functions such as x0y̅0and x̅0y0. In the proposed reversible binary comparator, the leaf nodes will consist of 2-bit reversible binary comparators. Each internal node (2-bit reversible binary comparator) of the binary tree receives the partial comparison results from the left and the right children and propagates the 2-bit output of the comparison to its parent. Finally, the root node which is also a 2-bit reversible binary comparator generates the 2-bit result of the comparison of the n-bit numbers x and y to evaluate whether x>;y or x0(x1(x>;y) and O2(x=y).