"AU: Timing Analysis Under Uncertainty
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw · International Conference on Computer Aided Design · 2003
Due to excessive reduction in the gate length, dopant concentrationsand the oxide thickness, even the slightest of variations inthese quantities can result in significant variations in the performanceof a device. This has resulted in a need for efficient andaccurate techniques for performing Statistical Analysis of circuits.In this paper we propose a methodology based on Bayesian Networksfor computing the exact probability distribution of the delayof a circuit. In case of large circuits where it is not possible tocompute the exact distribution, we propose methods to reduce theproblem size and get a tight lower bound on the exact distribution.