EFFICIENT METHOD FOR DESIGNING MODULO {2n ± k} MULTIPLIERS
Héctor Pettenghi, Sorin Cotöfană, Leonel A. Sousa · Journal of Circuits Systems and Computers · 2013
In this paper, an efficient method for designing memoryless modulo {2n ± k} multipliers is proposed, which can be used to compose larger residue number system (RNS) moduli sets. This technique includes a novel choice for the weights associated with the partial products of the inputs is used, which improves the performance of the resulting multipliers. Experimental results suggest that the use of this choice of input weights in the structure herein proposed, provides an average improvement of 36.3% in area-delay-product (ADP) in comparison with the related state-of-the-art. Furthermore, the structures presented in the state-of-the-art are also improved by 43.5% in ADP.