A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, J. Chang · 2006
A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes