Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1
Taeweon Suh, H.-H.S. Lee, Douglas M. Blough · IEEE Micro · 2004
This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.