Modeling and evaluating heterogeneous memory architectures by trace-driven simulation
Wei Wang, Qigang Wang, Wei Wei, Dong Liu · 2008
With the evolution of memory technologies, more types of memories are increasingly becoming available besides traditional DRAM. This paper focuses on the exploration how to organize heterogeneous memories for better performance. Two different models are introduced: Flat and Hierarchy. To evaluate our designs, the system bus trace is collected for trace-driven simulation. We use applications from SPEC jbb2005 and SPEC CPU2006 suite - typical server and desktop benchmark applications to compare the two models. It is shown that Hierarchical model can save much time in writing access and the average reading access time of it may longer or shorter than that of Flat according to the heterogeneous memory parameters. The Hierarchical model may also help to extend the life time of lower level memory while the Flat model can be used in a QoS enabled environment. Another contribution of our work is the recommended memory parameters in building the Hierarchical model.