A logic-based embedded DRAM with novel cell structure and dynamically adaptive refresh for long data retention, zero data availability penalty and high yield
Xiaoyong Xue, C. Meng, C.L. Dong, B. Chen, Yandan Lin, R. Huang, Qingtian Zou, Jin Gang Wu · 2013
Three techniques are proposed and verified on a logic-based 128kb embedded DRAM macro. Novel 2T gain cell of asymmetric junction increases data retention by 21X. Dynamically adaptive staggered refresh achieves zero data availability penalty and improves yield significantly. 60% smaller cell size than 6T SRAM and 25-30% refresh power reduction are obtained.