Performance Evaluation of AES Algorithm on Various Development Platforms
Chirag Ashwinkumar Parikh, Parimal A. Patel · 2007
With the rapid growth of low-cost, low-power handheld devices with wireless capability, more and more devices connect to wireless networks. This warrants secured data exchange and authentication to take place during the connection. 802.11i security scheme is becoming a de- facto standard of future WLAN, which uses AES algorithm in both encryption and authenticity of payload data. Cryptographic transformations of AES are computationally intensive, consuming significant power. Most of the published AES implementations target high- end products with multi-gigabit throughputs and have no regards for power consumption. Low-end products, including handheld devices like PDA rarely need more than 200 Mbps data transfer rate which necessitates alternative implementation of AES algorithm, with the aim of reducing power consumption and increasing the handsets' battery life. In this paper we study and compare the outcome obtained from implementing AES algorithm on various platforms. We present results obtained through profiling the implemented algorithm on platforms like FPGA, Desktop PC (Microsoft Visual Studio) and handheld device (UIQ SDK for Symbian OS along with Metrowerks CodeWarrior). Our comparison shows that the 32-bit hardware implementation of AES on FPGA supports the required throughput and consumes less power allowing fully charged PDA to remain connected to WLAN for a longer duration.