Map method for synthesis of logic circuits
M. Karnaugh · Electrical Engineering · 1954
THE MAP METHOD is a scheme for simplifying the derivation of logical forms for digital control and computing circuits. It comprises a number of improvements and extensions of a procedure suggested by E. W. Veitch,1who pointed out that each logical function may be represented uniquely by a rectangular array, the pattern of which leads to the synthesis of a simple, Boolean algebraic representation.