8-bit AES FPGA Implementation using Block RAM
Chi-Jeng Chang, Chi-Wu Huang, Hung-Yun Tai, Mao-Yuan Lin, Teng-Kuei Hu · 2007
An 8-bit data-path AES implementation was proposed recently by Tim Good [Tim Good, Mohammed Benaissa, "Very small FPGA application-specific instruction processor for AES", IEEE Trans. Circuit and System,vol. 53, no. 7, 2006.] as application-specific- instruction-processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.