Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder
Si-Yun J. Li, Tyler L. Brandon, Duncan G. Elliott, Vincent Gaudet · 2012
In this paper, we present an FPGA implementation of parallel-node low-density-parity-check convolution-code encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) LDPC convolutional-code encoder and decoder were implemented on an Alter a development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For a Eb/N0of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10-10and achieves an energy-per-coded-bit of 1.683 nJ based on raw power measurement results. The increase in Eb/N0can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for Eb/N0<; 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core.