BIST for logic and local interconnect resources in a novel mesh of cluster FPGA
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel · 2013
This paper presents new Built-In Self-Test (BIST) schemes for fault detection and diagnosis of Basic Logic Element (BLE) and intra-cluster (local) interconnect of a novel mesh of cluster FPGA. The proposed schemes avoid redundant test/diagnosis configurations by merging multiple configurations without losing diagnostic resolution. Efficiency of these schemes is calculated in terms of respective number of test/diagnosis configurations for the new FPGA. Results show that 50 BIST configurations are required for a complete test and diagnosis of the cluster. The testability aspects of this FPGA are explored in comparison with the classic clustered-mesh FPGA of the same parameters.