An FPGA-Based Novel Architecture for the Fixed-Point Binary Antilogarithmic Computation
Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar, Surya Prakash Gurunarayanan · 2014
Emerging embedded system applications require low power, fast and area-efficient implementation of complex arithmetic operations. Modern field-programmable gate array (FPGA) is a suitable candidate for implementing any reasonably complex architecture within minimal design time. Apart from the logic resources, most of the FPGAs contain hard-macro elements. By using a fixed-point data path, the available FPGA macro elements can be used to design an architecture that is much more complex. The realization of the complex arithmetic elements can be simpler by using a logarithmic number system. In this paper, a novel architecture and the FPGA realization of an antilogarithmic computing circuit is proposed. The proposed antilogarithmic circuit uses piecewise linear approximation method. The same architecture works for both the positive and negative binary numbers. A unique barrel-shifter is designed which shifts the input data to the left or right by the required amount. The proposed architecture is implemented in the Xilinx Virtex-5 xc5vfx70t device. The device utilization shows that the architecture utilizes a minimal FPGA resource. We have also performed error analysis of the approximation result. The error analysis shows that error associated with the positive numbers is 0.16% while that for the negative numbers is 0.8%. The error can be further minimized by taking more bits for the fractional bit representation.