System Level Design Exploration of JPEG 2000 with SoftSONIC Virtual Hardware Platform
Tero Rissa, Peter Y. K. Cheung, Wayne W. Luk · Conference proceedings · 2006
This paper presents development of a SoftSONIC virtual hardware platform for lossless high-resolution real-time JPEG 2000 encoding applications. It is demonstrated how a SystemC transaction level model of the platform can be used for automated architecture design exploration in three imaging application domains: medical, typical, and worst-case imaging. It is shown that with the virtual hardware platform it is possible to determine whether an architecture can sustain real-time processing requirements or not over 240 times faster than with RTL VHDL simulation. The virtual platform gives feedback of the design choices in memory and hardware resource usage and clock frequency requirements. These cannot be obtained from algorithmic C/C++ or Matlab model. In addition, by using a simple procedure to increase the parallelism of the system, our approach enables automated generation of customised architecture for varying processing requirements.