A versatile vector processor for multichannel speech recognition
R. Osborn · The Journal of the Acoustical Society of America · 1979
A 32-bit 122-ns cycle time computer has been developed for use as both a speech research tool and as the basis of a speech recognition product. It is structured as a single instruction stream device with three data buses independently controllable during each cycle. Function modules are connected between the buses. The timing and architecture are straightforward, allowing the addition of new functions as independent modules. Pipelines can be configured under software control and the instruction set is well structured and small, eliminating some of the complications of microcoded implementations. A standardized configuration is described which allows eight simultaneous channels of isolated word recognition in real time. The standardized configuration is currently being produced as part of a speech recognition product line.