A prototype platform for system-on-chip ADC test and measurement
Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann · 2009
An optimal solution for implementing ADC built-in-self-test into a SOC design is presented. ADC linear and dynamic testing occurs in parallel which reduces test time. A signal generator produces a ramp for linear histogram measurements and a sine-wave signal for dynamic tests. This platform permits a BIST design that is predominantly a digital solution and enables accurate testing using low silicon area.