A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder
Yuming Zhu, Yanni Chen, D.E. Hocevar, Manish Goel · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 2006
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version and the new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in IEEE 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps