Analyzing the Timing Error in Distributed Simulations of Asynchronous Computer Architectures.
Georgios K. Theodoropoulos, J.V. Woods · 1995
This paper discusses the time modelling problem in RTL distributed simulation models of asynchronous architectures written in occam. The results presented in the paper confirm that even if preemptions are allowed to occur, the timing error is not significant and it is acceptable at this level of simulation. 1. INTRODUCTION As VLSI technology advances and systems become larger, faster and more complex, timing problems in synchronous systems become increasingly severe and account for more and more of the design and debugging expense. Increased clock speeds make on-chip clock skew significant and interchip skew a major problem. In order to address those problems recently there has been a resurgence of interest in asynchronous design techniques which eliminate the need for global clocking. An asynchronous system may be designed as a set of functional modules each operating at its own rate and cooperating through communication. The synchronization of the functional modules is performed by...