TNODE: A low power sensor node processor for secure wireless networks
Goran Panić, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach‐Helmrich · 2013
In this paper we describe a sensor node crypto processor designed for use in wireless sensor networks with strong security demands. The presented system-on-chip is a mixed-signal processor-based design containing the hardware crypto accelerators (AES, ECC, SHA-1) that provide the means for secure communication in the network. The unique system architecture combines an asynchronous processor core with synchronous peripherals resulting in a low-power system operation. The designed chip integrates an embedded Flash memory and a 12-bit ADC making it a suitable solution for small-size sensor node devices. The paper describes the chip architecture and discusses the most important implementation and verification issues. Finally, the results of the chip measurement have been presented.