Simple hardware implementation of soft decision sequential decoder
Wenshu Hou, Yuzhong Jiang · 2009
A fast, simple hardware Fano sequential decoder with an efficient state scheme is presented. To maximize decoding performance, 8-bit soft decision decoding and a maximum possible backward depth equivalent to a whole frame is performed. The heart of the decoder is three independent encoders to generate the codewords to select branch metrics of predecessor node, current node and immediate successor node, which will be used in the rules of the Fano algorithm. Combined with bidirectional shift registers to store survivor path history, branch identification and branch metrics of each node, all the rules of the Fano algorithm are checked immediately and corresponding procedures like forward move, backward move and loosen threshold are implemented in the one clock cycle. A FPGA prototype of Fano decoder is built, and high speed is obtained by optimized state scheme to avoid additional time consuming read/write operations.