An effective measurement technique of level-2 cache performance for multicore embedded systems
M. F. Mridha, Abu S. Asaduzzaman, Aloke Kumar Saha · 2013
The state-of-the-art embedded systems are adopting multicore processors as multicore architecture provides high performance and better supports for computation intensive applications. Although cache improves the overall performance, designing multicore embedded systems with multilevel caches is a great challenge. Caches make thermal constraint crucial; parallel thread execution difficult; and timing unpredictability even worse. An effective early estimation technique can be very valuable to design level-2 cache (CL2) for multicore embedded systems. In this work, we propose a simulation based measurement technique to analyze the impact of CL2 on performance and power consumption to facilitate the design of future embedded systems. We model a quad-core system with two levels of caches (where CL2 is shared). By varying the locked CL2 cache size and total CL2 cache size, we run the simulation program using popular applications including MPEG-4 and MPEG-3. Simulation results reveal that up to 25% CL2 cache locking is helpful for the simulated system. It is also observed that mean delay per task and total power consumption decrease up to 41% and 52%, respectively, when cache size is increased and cache locking is applied.