Circuit verification based on diagnostic expert system methodology
Krzysztof W. Wawryn, A. Guziński · Electronics Letters · 1991
A circuit verification methodology for analogue CMOS IC design is presented. A diagnostic expert system in a feedback loop of the design system makes iterative improvements of the design until input performance specifications are satisfied. The system uses Horn clause knowledge representation and bidirectional inference mechanism with elements of hypothcsisation to make transistor sizes optimisations or to make topological changes within the circuit.