Test generation for circuits with embedded memories using SMT
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram · 2013
One of the important challenges in testing modern SOCs is the presence of small embedded memories. These memories are too small to employ memory BIST. Also, making these embedded memories scan-able or employing MBIST would increase the area overhead and/or test application time.