The GBT-FPGA core: features and challenges
Manoel Barros Marin, Sophie Baron, Sebastian S. Feger, P. Leitao, Elena Sorina Lupu, C. Soós, P. Vichoudis, K. Wyllie · Journal of Instrumentation · 2015
Initiated in 2009 to emulate the GBTX (Gigabit Transceiver) serial link and test the first GBTX prototypes, the GBT-FPGA project is now a full library, targeting FPGAs (Field Programmable Gate Array) from Altera and Xilinx, allowing the implementation of one or several GBT links of two different types: "Standard" or "Latency-Optimized". The first major version of this IP Core was released in April 2014. This paper presents the various flavours of the GBT-FPGA kit and focuses on the challenge of providing a fixed and deterministic latency system both for clock and data recovery for all FPGA families.