A Parallel Inference Machine
Tanaka · Computer · 1986
Presented here ia a parallel machine architecture, PIE, which the author expects to be the base for highly parallel inference machines. On a small sample of problems, experimenters have obtained speedups ranging from 20 to 170 times the single-processor system speeds for a system with 256 processors. The experiments show that the architecture has the potential to attain very high performance from parallel operation, but that speedup can be fairly low as well. Additional research will determine what speedup one can expect for particular classes of problems. Techniques need to be developed for achieving very high speedup on those classes of problems that currently exhibit poor speedup. Further study should focus on more precise evaluation, analysis, and building an experimental system. Finally, several improvements in the machine organization, such as pipeline control, associative search of clauses, garbage collection hardware, and support of secondary memory should be incorporated.