Simulation and verification II: from timed automata to DEVS models
Norbert Giambiasi, J.-L. Paillet, Frédéric Châne · Winter Simulation Conference · 2003
In this paper, we present the formal transformation of Timed Input/Output Automata into simulation models, expressed in the DEVS formalism. This transformation takes place in an approach of a validation of high-level specifications by simulation. The validation is based on the simulation of a coupled model built with the system to be controlled and the control specifications. An example of this approach is given in the paper.