An Architecture for High Speed Error Correction Circuitry
Tetsuo Iwaki, Tetsu Tanaka, Eiji Yamada, T. Okuda, T. Sasada · IEEE Translation Journal on Magnetics in Japan · 1993
An architecture for a high-speed Reed-Solomon decoder developed for digital VCRs is described. A maximum data rate of 16 MB/s and an error correction capability of 4-error- or 8-erasure-correction are realized using four-stage pipelines: a syndrome generator, a polynomial coefficient generator, a polynomial evaluator, and an error corrector. The polynomial coefficients are generated by a superscalar processor on a Galois field, which is controlled by instructions stored in ROM.