Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design
Masahiro Kaminaga, Takashi Watanabe, T. ENDO, Toshio Okochi · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2008
This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.