Instruction set mapping for performance optimization
M. Corazao, Mohammed Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey · 1993
Pe~ormunce optimization is the primary design goal in most digital signal processing (DSP) and numerically intensive applications. The problem of mapping high-level algorithmic descriptions for these applications to special-ized instruction sets has only recently begun to receive attention. In fact, the problem of optimizing performance has yet to be addressed directly. This paper introduces a new approach to instruction set mapping (and template matching in general) targeted toward pe~ormance optimi-zation. Several novel issues are addressed inc[uding par-tial matching and automatic clock selection. 1