Diagnose Failures Caused by Multiple Locations at a Time
Jing Ye, Yu Hen Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014
Fault diagnosis plays an important role in physical failure analysis and yield learning process. With tens of billions of transistors being integrated in one chip, multiple faults may exist. With multiple faults, fault masking and reinforcing effects may appear. They may cause the conventional single-fault-based diagnosis methods such as the single location at a time (SLAT) to be invalid. The popular SLAT approach fails if there are not enough SLAT patterns that can be explained by a single stuck-at fault. Moreover, a real silicon defect may behave as different fault models (DM) under different failing patterns, which may invalidate the SLAT approach that uses a single-fault model across all failing patterns. In this paper, we introduce the concept of fault element to support multiple fault models, and use a fault-element graph (FEG) to consider fault masking and reinforcing effects among multiple faults. Based on the FEGs of all failing patterns, the most likely fault locations and their fault elements are iteratively identified. Meanwhile, the FEGs are iteratively pruned to keep track of the remaining multiple fault effects until all the fault locations are identified and all the FEGs are reduced to null. Experiments demonstrate that the proposed diagnosis method can identify the locations of multiple faults even under DM with high diagnostic accuracy and resolution.