Energy-efficient dual-port cache architecture with improved performances
X. Chen, Hassan Bajwa · Electronics Letters · 2007
Low leakage current and area-efficient dual-port cache design, which uses isolation nodes and local sense amplifiers to facilitate dual-port accesses without duplicating the bit lines for the second port, is presented. Compared with conventional hardwired dual-port cache designs, the average bit line leakage current can be reduced by 50%.