Neuron machine: Parallel and pipelined digital neurocomputing architecture
Jerry B. Ahn · 2012
Neurocomputers supporting very-large-scale artificial neural networks are in demand. In this paper, a synchronous digital neurocomputing architecture called Neuron Machine is proposed. In this architecture, memories are arranged such that data for a large number of neural connections can be stored and accessed simultaneously. This memory structure enables both parallel computation of multiple connections and pipelining of a series of computation stages, thereby exploiting a large amount of parallelism. In addition, there are no fundamental limitations on the network size and topology of the artificial neural networks that it can compute. The proposed architecture was implemented on a field-programmable gate array (FPGA), and it was demonstrated that a learning speed in excess of 70 giga connection updates per second (GCUPS) can be achieved using a single chip. This architecture can be used to implement large-scale general-purpose neuro-computers or neurochips in real-time applications.