System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV
Kouichi Kumagai, Changqi Yang, Hitoshi Izumino, Nagato Narita, Keisuke Shinjo, 政治 岩下, Y. Nakaoka, Tatsurou Kawamura, Hideo Komabashiri, Tsukasa Minato, Atsushi Ambo, Teruhiko Suzuki, Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga, Yusaku Mabuchi, Kenji Yoshida · 2006
System-in-silicon (SiS) is a multi-chip architecture to realize wide bandwidth communication between logic and memory with low power. The application of SiS to H.264/AVC motion estimation is presented. DRAM is integrated with 23.1 Gb/s bandwidth and 1.6pJ/b data transfer efficiency, realizing real-time 1080HDTV processing with 263.1GB/s. The authors present a system-in-silicon architecture with 1024b inter-chip bus to provide high-bandwidth low-power connectivity between logic and memory. The highly parallel architecture also allows low frequency (25MHz) operation while achieving real-time motion estimation for 1080HDTV. The solution achieves the required 23.1 Gb/s bandwidth and associated processing for motion estimation at a power level of 190mW