Design methodologies of comparators based on parallel hardware algorithms
Kiyoshi Furuya · 2010
Various comparator designs that are suitable for current device technology are shown. The designs are based on LSB-first or MSB-first approaches. Linear operation time designs are derived as the first step. O(log n) operations time with O(n) or O(n log n) hardware cost are attained by parallel implementation of prefix operations and reductions.