Optimal processor interconnection topologies
Mamoru Maekawa · International Symposium on Computer Architecture · 1981
This paper proposes the optimal processor interconnection topologies for parallel processing. The topologies are optimal with respect to the performance/cost ratio under the controlled message transfer delay and can be systematically constructed for an arbitrary number of processors. The addition and the deletion of processors are simple and done with the minimum number of bus reconnections. The message transfer delay, as well as the reliability, can be controlled by changing the degree of the topology. Owing to these properties, the optimal interconnection topologies are suitable for many kinds of parallel processing systems and algorithms.