Improved decoder design for LDPC codes based on selective node processing
Sachin Singh Khati, Pooja Bisht, Subhash Chandra Pujari · 2012
This paper proposes a low complexity decoder design for low density parity check (ldpc) codes. The design primarily comprises a novel decoding algorithm and semi parallel high throughput architecture. Based on the observation that nodes with high log likelihood ratio provide almost same information in every iteration and can be deemed as static, we propose an algorithm in which the parity check matrix H is updated to a reduced form every time a static node is encountered resulting in lesser number of computations in subsequent iterations. Also the design greatly benefits from the area efficient semi-parallel architecture and the various improvisations introduced at different levels of abstraction in the decoder design. The decoder design is implemented for a ldpc code compliant with WLAN 802.11n standard using sum product algorithm. The simulation results showed a significantly higher throughput with an easily controllable increase in bit error rate.