KIM200: a tagged-RISC architecture for gallium arsenide implementation
Jean-Claude Heudin, Christophe Metivier · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1990
This paper describes a new RISC architecture being designed to take advantage of GaAs technology for high performance symbolic processing. First, we present our top-down methodology which starts from the study of applications requirements, technology constraints, and concludes with the choice of the most suitable architecture. Then, next paragraphs describe carefully the architecture and its originalities. It can be summerized as a tagged-RISC embedded processor, which is able to operate with a 200 Mhz clock rate. As a conclusion, we give performance goals and simulation results.