A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts
Shih‐Hung Chen, Hang-Ting Lue, Yen-Hao Shih, Chieh-Fang Chen, Tzu‐Hsuan Hsu, Yanru Chen, Yi‐Hsuan Hsiao, Shih-Cheng Huang, Kuo-Pin Chang, Chih-Chang Hsieh, Guan-Ru Lee, Alfred T. H. Chuang, Chih‐Wei Hu, Chia-Jung Chiu, Lo Yueh Lin, Hong-Ji Lee, Feng-Nien Tsai, Chin-Cheng Yang, Tahone Yang, Chih-Yuan Lu · 2012
We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BL's (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2Mcontacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.