Floorplanning and topology generation for application-specific network-on-chip
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto · 2010
Abstract — Network-on-Chip(NoC) architectures have been proposed as a promising alternative to clas-sical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation prob-lem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Fi-nally, we allocate paths to minimize power consump-tion. The experimental results show our algorithm is effective for power saving. I.