Reduced‐complexity local switch based multi‐mode QC‐LDPC decoder architecture for Gbit wireless communication
Sabooh Ajaz, Hyeonggeon Lee · Electronics Letters · 2013
A low‐complexity low‐power multi‐mode quasi‐cycle low‐density parity check decoder architecture for 60‐GHz Gbit wireless communication is presented. A novel, dynamic column shifting scheme is introduced for a multi‐mode architecture that provides a low complexity and fixed throughput across all rates. Novel low‐complexity local switch architecture and its control values are described to implement the dynamic shifting scheme. Post‐layout results show that the proposed architecture has low power consumption at high throughputs. It reduces about 57% memory and 31% area requirement compared to previously reported architecture.