A fast method for timing verification that uses the conditions that cause changes in the output values of gates
Atsushi Ohnishi, Yuji Sugiyama · Systems and Computers in Japan · 2000
This paper discusses a fast method for timing verification which uses the conditions that cause changes in the output value of gates in a combinational logic circuit. The methods proposed previously derive the conditions that make a circuit behave correctly and incorrectly, but the new method in this paper derives only the latter. The new method also efficiently decides whether the derived condition is satisfied or not. © Scripta Technica, Syst Comp Jpn, 32(1): 38–44, 2001